FPGA IP workspace

Design FPGA IP cores directly in VS Code.

Design IP cores and register maps visually, keep the design in readable YAML, then generate and build RTL without leaving VS Code.

Install for VS Code Read the quick start
VHDL SystemVerilog Vivado Quartus
IPCraft — IP Core Editor
IP Core visual canvas with ports and bus interfaces
busInterfaces:
  - name: s_axi
    busType: AXI4-Lite
    mode: slave
Development workflow

From specification to implementation.

Describe the design once, then use the same information to generate HDL, tests, documentation, and Vivado or Quartus projects.

Describe

Define ports, interfaces, address blocks, registers, and fields in visual editors. Every change remains visible in reviewable YAML.

Generate

Generate VHDL or SystemVerilog, bus wrappers, register files, Cocotb tests, documentation, and vendor project files.

Verify and build

Check generated HDL, inspect captured data, run simulations, and build with Vivado or Quartus from VS Code.

Visual editors

A dedicated editor for each part of the specification.

IPCraft provides separate editors for the IP core, register layout, and captured data. They all use the same YAML design files.

IPCraft — IP Core Editor
IP Core visual canvas with ports and bus interfaces
Architecture

Design an IP core on a visual canvas.

Place clocks, resets, ports, bus interfaces, and parameters. Select an item to edit its properties in the inspector.

Explore the IP Core editor →
Register design

Define registers and bit fields visually.

Edit blocks, registers, and bit fields in keyboard-friendly tables with a visual bit layout that stays synchronized with YAML.

Learn memory-mapped registers →
Hardware data

Inspect captured data against register definitions.

Map CSV captures and literals onto register definitions, then decode, combine, and inspect values in a visual workspace.

Explore the Data Inspector →
IP Core visual canvas with ports and bus interfaces
Architecture

Design an IP core on a visual canvas.

Place clocks, resets, ports, bus interfaces, and parameters. Select an item to edit its properties in the inspector.

Explore the IP Core editor →
Memory map editor with register and bit-field tables
Register design

Define registers and bit fields visually.

Edit blocks, registers, and bit fields in keyboard-friendly tables with a visual bit layout that stays synchronized with YAML.

Learn memory-mapped registers →
Data Inspector visual workspace with captured hardware values
Hardware data

Inspect captured data against register definitions.

Map CSV captures and literals onto register definitions, then decode, combine, and inspect values in a visual workspace.

Explore the Data Inspector →
Capabilities

Support for the full FPGA project workflow.

IPCraft automates the repetitive work between formats and tools, so you can focus on design decisions.

Vendor project generation

Generate complete RTL projects with bus wrappers, constraints, packaging metadata, testbenches, and scripts for your chosen toolchain.

AXI4-LiteAvalon-MMVivadoQuartuscocotb

Import existing designs

Reverse-engineer VHDL entities, Platform Designer components, and Vivado IP-XACT metadata into an IPCraft specification instead of beginning from a blank file.

VHDL entity_hw.tclcomponent.xml

Bring your own templates

Generation is not locked to IPCraft's built-in HDL templates. A scaffold pack is a plain directory of Nunjucks templates, referenced from the IP Core spec, that overrides any built-in template by file name — replace one file or the entire set.

scaffold_packNunjucks .j2Template overrides
Read the scaffold packs guide →

Readable, version-controlled specification

Keep compact, versionable YAML at the center while visual edits preserve comments and numeric formatting.

Next steps

Get started with IPCraft.

Install IPCraft, create an IP Core with a register map, and generate a working project from your first interface.

Install IPCraft View on GitHub